Electronics Circuits Design

Showing posts with label Verilog. Show all posts

Wednesday, February 20, 2008

Comprehensive Verilog Tutorials

Chapter 1: Introduction & Overview of modules and procedures
Chapter 2: Language Basics, Net & Register Data Types
Chapter 3: Verilog Simulations & Display Commands
Chapter 4: Continuous Assignments, Time Delays & Timescales
Chapter 5: Verilog Operators, Timing Controls, Decisions & Looping Statements
Chapter 6: RTL Models of Combinational Logic, Interactive Debugging
Chapter 7: RTL models of Sequential Logic, Behavioral Models of RAMs & ROMs
Chapter 8: Modeling Structural Designs
Chapter 9: Blocking & Non Blocking Assignments, State Machine Designs
Chapter 10: File I/O, Test benches, Introduction to Synthesis Design Flows
Chapter 11: Additional Behavioral Commands, Verilog Strength Handling
Chapter 12: Verilog Gate Primitives, user defined Primitives
Chapter 13: Specify Blocks, SDF Back Annotation
Chapter 14: Switch Primitives, Passive Device Modeling

Thanks to Jim Blake of Centillium, Raghav Santhanam of Synopsys & Pedro of Texas A&M University for the Tutorials and other numerous contributions.

Comparison of VHDL to Other Hardware Description Languages

VHDL Disadvantages

VHDL is verbose, complicated and confusing
Many different ways of saying the same thing
Constructs that have similar purpose have very different syntax (case vs. select)
Constructs that have similar syntax have very different semantics (variables vs signals)
Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)

VHDL Advantages

VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.
VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.
VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.
VHDL has a rich collection of datatypes
VHDL is a full-featured language with a good module system (libraries and packages).
VHDL has a well-defined standard.

VHDL and Other Languages

VHDL vs Verilog
- Verilog is a "simpler" language: smaller language, simple circuits are easier to write
- VHDL has more features than Verilog
  - richer set of data types and strong type checking
  - VHDL offers more flexibility and expressivity for constructing large systems.
- The VHDL Standard is more standard than the Verilog Standard
  - VHDL and Verilog have simulation-based semantics
  - Simulation vendors generally conform to VHDL standard
  - Some Verilog constructs don't simulate the same in different tools
- VHDL is used more than Verilog in Europe and Japan
- Verilog is used more than VHDL in North America
- South-East Asia, India, South America - More Democratic
VHDL vs SystemC
- System C looks like C —familiar syntax
- C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?
- If you think VHDL is hard to synthesize, try C....
- SystemC simulation is slower than advertised
VHDL vs Other Hardware Description Languages
- Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.
- SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.
- Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

Verilog rules that can save your breath !

This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rules that will save you headaches if you follow, and how a Verilog file should be layed out.

Rules:

If you don't know what hardware the code you just wrote is, neither will the synthesizer.
Remember that Verilog is a Hardware Description Language (HDL) and as such it describes hardware not magical circuits that you can never actually build.
You should be able to draw a schematic for everything that you can write Verilog for.
Be sure to know what part of your circuit is combinational and which parts are sequential elements. If you do not know or the code is written to be too hard to figure this out, the synthesizer will probably not be able to figure it out either. I recomend making the combinational logic very separate from sequential logic. This prevents errors later. It also prevents level high latches from being synthesized where you meant to have flip-flops. I also recomend having a naming convention such that you can tell what is a state holding element at all times. I use "_f" post-pended to all registers that are flip-flops.
I recomend having a style for your inputs and outputs. I list them in the following order: outputs, inouts, special inputs such as clk and reset, inputs.
When instantiating a module, always put the names of the signals that you are conecting to inside of the module with the notations where you have period, module signal name, thing you are connecting. This prevents errors when you change underlying modules or someone resorts the parameters.
Unlike a language like C which is rather strongly typed, in Verilog, which is also strongly typed, everyting is of the same type and it is easy to reorder parameters and not get errors becasue everything is just a wire.
Example of wrong module instantiation: nand2 my_nand(C, A, B);
Example of correct module intantiation: nand2 my_nand(.out(C), .in1(A), .in2(B));
Make your circuit synchronous whenever possible. Synchronous design is much easier than asynchronous.
Also reduce the number of clock domains and clock boundaries whenever possible.
Also remember that crossing clock domains in FPGAs is difficult because LUT's glitch in different ways than normal circuits. This causes problems with asynchronous circuits.

Verilog files should be laid out like this..

define consts
declare outputs (these are _out)
declare inouts if any (these are _inout)
declare special inputs such as clk and reset
declare inputs (these are _in)
declare _all_ state (these are _f)
declare inputs to state with (these have same name as state but are _temp)
declare wires (naming not restricted except connections of two instantiated modules are usually of the form A_to_B_connection)
declare 'wire regs' (naming not restricted except connections are usually of the form A_to_B_connection and variables that are going to be outputs, but still need to be read and you don't want inouts get _internal postpended)
do assigns
do assigns to outputs
instantiations of other modules
combinational logic always @'s are next
do the always @ (posedge clk ...) and put reset values here and assign _temps to _f's (ie state <= next_state). I personally think that there should be no conbinational logic inside of always @(posedge clk's) with the exception of conditional assignment (write enables) becasue all Verilog synthesizers understand write enables on flip-flops.

Verilog Question

A 3:1 mux has three data inputs D0, D1 and D2, two select inputs S0 and S1 and one data output Y.

The value of output Y is calculated as follows:
Y = D0 if S0 = 0 and S1 = 0
Y = D1 if S0 = 1 and S1 = 0
Y = D2 if S1 = 1 (the value S0 doesn't matter)

Write a Verilog module for the 3:1 multiplexer using dataflow style modelling (assign) that implements the sum-of-products equation for Y.
Write a Verilog module for the 3:1 multiplexer that uses the "?" operator. Again use a dataflow style for your code (ie, use "assign" to set the values of your signals).
Write a Verilog module for the 3:1 multiplexer that uses the "case" statement. Remember that a "case" statement can only appear inside of a behavioral block.

Verilog Awareness

Differentiate between Inter assignment Delay and Inertial Delay ?

What are the different State machine Styles ? Which is better ? Why and when do we use one ove the other? Explain Disadv. and Adv.?

What is the difference between the following lines of code ?

reg1<= #10 reg2 ;
reg3 = # 10 reg 4 ;

What is value of Var1 after the following assignment ?

reg Var1;
initial begin
Var1<= "-"
end

What is the output of the below code?

module quest_for_out();
integer i;
reg clk;
initial begin
clk = 0;
#4 $finish;
end
always #1 clk = !clk;
always @ (posedge clk)
begin : FOR_OUT
for (i=0; i < i =" i">
if (i == 5) begin
disable FOR_OUT;
end
$display ( "Current i : %g" ,i);
end
end
endmodule

What is the output of the below code?

module quest_for_in();
integer i;
reg clk;
initial begin
clk = 0;
#4 $finish;
end
always #1 clk = !clk;
always @ (posedge clk)
begin
for (i=0; i < i =" i">
if (i == 5) begin
disable FOR_IN;
end
$display ( "Current i : %g" ,i);
end
end
endmodule

Verilog Awareness

Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ?
What is the difference between blocking and nonblocking assignment? Explain with a simple example?
What is the difference between wire and a reg data type?
Write code for async reset D-Flip-Flop, Shift Register.
Write code for 2:1 MUX using different coding styles.
Write code for parallel encoder and priority encoder.
Different "case" usage styles! Explain.
What is the difference between === and == ?
Why is defparam used for ?
What is the difference between unary operator and logical operator ?
What is the difference between task and function ?
What is the difference between transport and inertial delays?
What is the difference between casex and case statements ?
What is the difference between $monitor and $display ?
What is the difference between compiled, interpreted, event based and cycle based simulator ?

Verilog Blocking Vs Non Blocking, Myths and Facts

I know people who swear by blocking and some who swear by non-blocking.So here are some thoughts.There is very little difference between non-blocking and blocking in speed and no errors if done correctly either way.The main differences are:Some people like non-blocking because you can tell that a reg on the left hand side of <= is going to be a flip flop after synthesis./* example 1a */ reg a,b,c; always @(posedge clock) begin b <= a; /* b and c will be flip flops */ c <= b; end /* example 1b */ reg a,b,c; always @(posedge clock) begin c <= b; b <= a; /* b and c will be flip flops */ end /* example 2a */ reg a,b,c; always @(posedge clock) begin b = a; c = b; /* Only c will be a flip flop,b will go away after synthesis. *//* We could delete the 2 above assignments and replace it with c=a;b=a; In fact, b is the same as c and can be eliminated.*/end /* example 2b */ reg a,b,c; always @(posedge clock) begin c = b; b = a; /* Both b and c will be flip flops, because these 2 lines are reversed.*/ end Example 1a, 1b and 2b are functionally the same.Example 2a is functionally different from 2b just because the order of the statements. Some people like blocking because it takes less memory in the simulator. /* example NON-BLOCKING_MEMORY */ reg a,b,c; always @(posedge clock) begin /* b will require 2 memory locations*/ b <= a;/*<---because this b memory location will hold value of a */ c <= b;/*<---and this b memory location will hold value of b before the posedge*/ end /* example BLOCKING_MEMORY */ reg a,b,c; always @(posedge clock) begin // b will require ONLY 1 memory location c = b; b = a; end Note that I am talking about SIMULATOR memory, not flip-flop count after synthesis. In most cases, the simulator has to remember the value before and after posedge clock if a reg goes between modules in order in order to "execute modules in parallel", so there may be no savings.Some people like blocking because you can see sharing of resources more readily. // example 5reg [15:0] a,b,c,d,e,f,j,k,g,h; reg [16:0] x,y,z; always @(posedge clock) begin x = a + b + c + d + e + f + j + k; y = x + g; z = x + h; end // example 6reg [15:0] a,b,c,d,e,f,j,k,g,h; reg [16:0] y,z; always @(posedge clock) begin y <= (a + b + c + d + e + f + j + k) + g; z <= (a + b + c + d + e + f + j + k) + h; end Even the cheapest synthesizer should share adder logic in example 5, but a slightly smarter synthesizer is required in example 6.You will have fewer problems with race conditions in SIMULATION if you always use non-blocking assignments inside always @(posedge clock) blocks where you want to have flip-flops.file xyz.v : module xyz(a,b,clk); input b,clk; output a; reg a; always @(posedge clk) a = b; endmodule file abc.v : module abc(b,c,clk); input c, clk; output b; reg b; always @(posedge clk) b = c; endmodule Some of the simulators out there will execute module abc first and then module xyx. This effectively transfers contents of c to a in ONE clk cycle. This is what some people refer to as a simulator race conditon. Other simulators will execute module xyz and then module abc giving a different simulation result. In some simulators, order of execution cannot be controlled by users.

synthesizable Verilog from behavioral constructs - 1

Modifying a behavioural Verilog wait statement to make it synthesizable.Behavioural:command1;wait (x != 0);command3;Synthesizable:case (state)0 : begincommand1;if (x != 0) command3;else state <= 1;end1 : if (x != 0) // wait until this is truecommand3;endcaseYou also need to add the variable state, reg state. If a cycle delay between command1 and command3 does not matter, then the following is simpler, but not identical to the original:case (state)0 : begincommand1;state <= 1;end1 : if (x != 0) // wait until this is truecommand3;endcaseThe latter approach is preferred in many cases for coding simplicity.Note: in general commandi refers to a block of commands. It is assumed there is an appropriate clock for the case statement state machines. Care is required in setting appropriate reset states, initialization, and completion of use of a state machine:* Is there a signal to tell the state machine to begin?* Does a done signal go high, signalling the state machine has finished?* When it is not in operation, does the state machine idle correctly? Does it change signal values shared with other code? Does it set outputs from it to appropriate idling values?* Is the state machine reset to the idle state by a reset signal?* Ensure that you initialize all registers.* Ensure that your state register has the correct bit width - if it is too small, assigning a larger state value will just return it to an earlier state.

Verilog Awareness - Interview Questions

Q: Given the following Verilog code, what value of "a" is "displayed"?
always @(clk)begina = 0;a <= 1; $display(a);endQ: Given the following snippet of Verilog code, draw out the waveforms for "clk" and "a".
always @(clk)begina = 0;#5 a = 1;endQ: What is the difference between the following two lines of Verilog code?
#5 a = b;a = #5 b;Q: Write Verilog to provide a divide-by-3 clock from the standard clock.Q: What is the difference between:
c = foo ? a : b;andif (foo) c = a; else c = b;Q: Using the given, draw the waveforms for the following (each version is separate, i.e. not in the same run):
reg clk;reg a;always #10 clk = ~clk;(1) always @(clk) a = # 5 clk;(2) always @(clk) a = #10 clk;(3) always @(clk) a = #15 clk;Now, change to a wire, and draw for:(4) assign #5 a = clk;(5) assign #10 a = clk;(6) assign #15 a = clk;