Electronics Circuits Design

Showing posts with label VHDL. Show all posts

Wednesday, February 20, 2008

VHDL Interview Question(s)

What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?
What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
For each of the architectures muruku 1. . . muruku 4, answer the following questions.
INSTRUCTIONS:
Is the code legal VHDL?
If the code is legal VHDL:
Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit.
Answer whether the code is synthesizable.
If the code is synthesizable, answer whether it adheres to good coding practices.If the the code is not legal, not synthesizable, or does not follow good coding practices, explain why.
entity sumit isport (a, b, clk : in std_logic;z : out std_logic);end schreyer;architecture main of sumit issignal m : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not m; end if; end process; end main;
Muruku 1
architecture muruku_1 of sumit issignal m : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; z <= not m; end if; end process; end muruku_1;
Muruku_X
architecture muruku_X of sumit issignal m, p : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= p; end if; end process; p <= not m; end muruku_X;
Muruku_2
architecture muruku_2 of sumit issignal m, p : std_logic;beginif (a or b) = ’1’ generatem <= ’1’; end generate; if (a or b) = ’0’ generate m <= ’0’; end generate; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not p; end if; end process; end muruku_2;
Muruku_3
architecture muruku_3 of sumit isbeginprocessbeginwait until rising_edge(clk);wait until rising_edge(clk);z <= not (a or b); end process; end muruku_3;
Muruku_4
architecture muruku_4 of sumit issignal m, p : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; z <= not p; end muruku_4;

The Good, the Bad, and the Unsynthesizable - Interview Questions in vhdl

For each of the code fragments, answer whether the code is legal VHDL.
If the code is legal VHDL, answer whether it is synthesizable.
If the code is synthesizable:
answer whether it represents good coding practices.
answer whether the signal w or y is combinational, a latch, or a flip-flop.
If the the code is not legal, is not synthesizable, or does not follow good coding practices, explain why.
The signals are declared as follows:
a, b, c, d, w : std logic
m, y : unsigned(15 downto 0)
process (a, b) beginif a = '1' thenw <= b;end if;end process;
process (a, c) beginif a = '0' thenw <= c;end if;end process;
Answer:unsynth: single assignment rule — can't have multiple processes driving the same signal
process beginwait until rising_edge(a);w <= not w;end process;
Answer:good: w=flop // or bad coding style, because state machine without reset
b <= a;if b = '1' generatew <= c;end generate;if b = '0' generatew <= d;end generate;
Answer:illegal: dynamic test in generate
process beginw <= '0';wait until (a = '0');p: loopwait until rising_edge(b);next p when (a = '1');w <= c xor d;end loop;end process;
Answer:unsynth: different wait conditions
process (m) beginfor i in 15 downto 0 loopif 3 >= i theny(i) <= '0';elsey(i) <= m(i-3);end if;end loop;end process;
Answer:good: y = comb
process beginwait until rising_edge(a);if b = '1' thenwait until rising_edge(a);w <= b;elsew <= c;end if;end process;
Answer:good: w=flop

Comparison of VHDL to Other Hardware Description Languages

VHDL Disadvantages
VHDL is verbose, complicated and confusing
Many different ways of saying the same thing
Constructs that have similar purpose have very different syntax (case vs. select)
Constructs that have similar syntax have very different semantics (variables vs signals)
Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)VHDL Advantages
VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.
VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.
VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.
VHDL has a rich collection of datatypes
VHDL is a full-featured language with a good module system (libraries and packages).
VHDL has a well-defined standard.VHDL and Other Languages
VHDL vs Verilog
Verilog is a "simpler" language: smaller language, simple circuits are easier to write
VHDL has more features than Verilog
richer set of data types and strong type checking
VHDL offers more flexibility and expressivity for constructing large systems.
The VHDL Standard is more standard than the Verilog Standard
VHDL and Verilog have simulation-based semantics
Simulation vendors generally conform to VHDL standard
Some Verilog constructs don't simulate the same in different tools
VHDL is used more than Verilog in Europe and Japan
Verilog is used more than VHDL in North America
South-East Asia, India, South America - More Democratic
VHDL vs SystemC
System C looks like C —familiar syntax
C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?
If you think VHDL is hard to synthesize, try C....
SystemC simulation is slower than advertised
VHDL vs Other Hardware Description Languages
Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.
SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.
Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

VHDL Online books

http://esd.cs.ucr.edu/labs/tutorial/VHDL_Page.html
Books
Tutorials
Examples
Tools
Download
Others
VHDL Tutorial: Learn by Example
Basic Logic Gates
Combinational Logic Design
Typical Combinatinal Logic ComponentsLatch and Flip-Flops
Sequential Logic Design
Typical Sequential Logic Componentshttp://esd.cs.ucr.edu/labs/tutorial/

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