ASIC equivalent gates for Virtex in digital elctronics

4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3

If you do some quick math, one can calculate the typical ASIC gates for a
Virtex 1000, which has a 64x96 CLB array:
( 64*96 CLB )* ( 2 Slices/CLB )* ( 20 Gates/Slice ) = 245,760 Gates

FPGA & ASIC based design

The main diferrence between ASIC and FPGA based design is in the Back-end.
In FPGAs there is not much activities in back end.

FPGA flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.

ASIC flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> EXTRACT RC VALUES -> DRC, LVS,etc., -> LIBRARY VENDOR SPECIFIC FILE FORMAT

Application Specific Integrated Circuit ( ASIC )

An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized for a particular use (equipment or project), rather than serving for general-purpose use. For example, a chip designed solely to run a cash register is an ASIC. In contrast, a microprocessor is not application-specific, because users can adapt it to many purposes.

The initial ASICs used gate-array technology.

The British firm Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customisation occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

In the late 1980s, the availability of logic synthesis tools (such as Design Compiler) that could accept hardware description language descriptions using Verilog and VHDL and compile a high-level description into to an optimised gate level netlist brought "standard-cell" design into the fore-front. A standard-cell library consists of pre-characterized collections of gates (such as 2 input nor, 2 input nand, invertors, etc.) that the silicon compiler uses to translate the original source into a gate level netlist. This netlist is fed into a place and route tool to create a physical layout. Routing applications then place the pre-characterized cells in a matrix fashion, and then route the connections through the matrix. The final output of the "place & route" process comprises a data-base representing the various layers and polygons in GDS-II format that represent the different mask-layers of the actual chip.

Finally, designers can also take the "full-custom" route in implementing an ASIC. In this case, an individual description of each transistor occurs in building the circuit. A "full-custom" implementation may function five times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker and with less risk of errors, than the "full-custom" choice.

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) has increased from 5000 gates to 20 million or more. Modern ASICs often include 32-bit processors and other large building-blocks. Many people refer to such an ASIC as a SoC - System on a Chip.

The use of intellectual property (IP) in ASICs has become a growing trend. Many ASIC houses have had standard cell libraries for years. However IP takes the reuse of designs to a new level. Designers of most complex digital ICs now utilise computer languages that describe electronics rather than code. Many organizations now sell tested functional blocks written in these languages. For example, one can purchase CPUs, ethernet or telephone interfaces.

For smaller designs and/or lower production volumes, ASICs have started to become a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable. Some SoCs consist of a microprocessor, various types of memory and a large FPGA.