sequential circuit

• In order for the circuit shown above to operate correctly what constraints on tH and tS are necessary? Express them in terms of tCD, tPD and the clock period.

• What is the minimum clock period at which this circuit can be clocked and still be guaranteed to work? Express your answer in terms of tH, tS, tCD and tPD. Assume that timing constraints that do not depend on the clock period are met.

• For just this question suppose there is skew in the CLK signal such that the rising edge of CLK arrives at the flip-flop labeled F1 1ns before it arrives at the other three flip-flops. Assume that hold times are not violated. How does this change the minimum clock period at which the circuit above can be clocked and still be guaranteed to work?

sequential circuit

• Assuming that the clock period is 25ns, what is the maximum setup time for the registers for which this circuit will operate correctly?

• Assuming that the clock period is 25ns, what is the maximum hold time for the registers for which this circuit will operate correctly?

sequential circuit

• What is the smallest value for the ROM's contamination delay that ensures the necessary timing specifications are met?

• Assume that the ROM's tCD = 3ns. What is the smallest clock period that ensures that the necessary timing specifications are met.

sequential circuit 2

Calculate timing parameters for the system as a whole taking into account d1 and d2. Don't make any assumption about the relative sizes of the two delays.

sequential circuit 1

• What is the smallest clock period for which the circuit still operates correctly?
• By removing the pair of inverters and connecting the Q output of the left register directly to the D input of the right register, if the clock period could be adjusted appropriately, would the optimized circuit operate correctly? If so, explain the adjustment to the clock period that would be needed.
• When the RESET signal is set to "1" for several cycles, what values are loaded into the registers? (Give values for S0 and S1)
• Assuming the RESET signal has been set to "0" and will stay that way, what value will with the registers have after the next clock edge assuming the current values are S0=1 and S1=1?
• Now suppose there is skew in the CLK signal such that the rising edge of CLK always arrives at the left register exactly 1ns before it arrives at the right register. What is the smallest clock period for which the FSM still operates correctly?

sequential circuit 3

Calculate the timing parameters (tS, tH, tCD, tPD, tCLK) for this system as a whole.