Verilog Awareness

Differentiate between Inter assignment Delay and Inertial Delay ?

What are the different State machine Styles ? Which is better ? Why and when do we use one ove the other? Explain Disadv. and Adv.?

What is the difference between the following lines of code ?

1. reg1<= #10 reg2 ;
2. reg3 = # 10 reg 4 ;

What is value of Var1 after the following assignment ?

1. reg Var1;
2. initial begin
3. Var1<= "-"
4. end

What is the output of the below code?

1. module quest_for_out();
2. 
   
3. integer i;
4. reg clk;
5. 
   
6. initial begin
7. clk = 0;
8. #4 $finish;
9. end
10. 
    
11. always #1 clk = !clk;
12. 
    
13. always @ (posedge clk)
14. begin : FOR_OUT
15. for (i=0; i < i =" i">
16. if (i == 5) begin
17. disable FOR_OUT;
18. end
19. $display ( "Current i : %g" ,i);
20. end
21. end
22. endmodule

What is the output of the below code?

1. module quest_for_in();
2. 
   
3. integer i;
4. reg clk;
5. 
   
6. initial begin
7. clk = 0;
8. #4 $finish;
9. end
10. 
    
11. always #1 clk = !clk;
12. 
    
13. always @ (posedge clk)
14. begin
15. for (i=0; i < i =" i">
16. if (i == 5) begin
17. disable FOR_IN;
18. end
19. $display ( "Current i : %g" ,i);
20. end
21. end
22. endmodule