Free E-Book: ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)

ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)

by Richard Munden
"As large and complex as today's FPGAs are, they always end up on a board..." ( more)

Key Phrases: path delay section, negative timing constraints, skew violation, Free Model Foundry, Output Glitch Detection Variables, Vital Memo (more...)

Review
Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop inter operable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.

Randy Harr, Sevni Technology

This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.

Hardy Pottinger, University of Missouri-Rolla

Book Description
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

• Provides numerous models and a clearly defined methodology for performing board-level simulation.
• Covers the details of modeling for verification of both logic and timing.
• First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Download ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling.Morgan.Kaufmann.pdf

Algorithms and High level models

For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract state machines, algorithmic state machines, etc.
For designs with trivial control flow (e.g. every parcel of input data undergoes the same computation), data-dependency graphs are a good way to describe the algorithm.
For designs with a small amount of control flow (e.g. a microprocessor, where a single decision is made based upon the opcode) a set of data-dependency graphs is often a good choice.

1. When creating an algorithmic description of your hardware design, think about how you can represent parallelism in the algorithmic notation that you are using, and how you can exploit parallelism to improve the performance of your design.
2. Flow charts and various flavors of state machines, everything that you might 've learned about these forms of description are also applicable in hardware design. In addition, you can exploit parallelism in state machine design to create communicating finite state machines. A single complex state machine can be factored into multiple simple state machines that operate in parallel and communicate with each other.
3. In software, the expression: (((((a + b) + c) + d) + e) + f) takes the same amount of time to execute as: (a + b) + (c + d) + (e + f). But, remember: hardware runs in parallel. In algorithmic descriptions, parentheses can guide parallel vs serial execution.
4. Data dependency graphs capture algorithms of datapath-centric designs.Datapath-centric designs have few, if any, control decisions: every parcel of input data undergroes the same computation.
   

There are many different types of high-level models, depending upon the purpose of the model and the characteristics of the design that the model describes. Some models may capture power
consumption, others performance, others data functionality. High-level models are used to estimate the most important design metrics very early in the design cycle. If power consumption is more important than performance, then you might write highlevel models that can predict the power consumption of different design choices, but which has no information about the number of clock cycles that a computation takes, or which predicts the latency inaccurately. Conversely, if performance is important, you might write clock-cycle accurate high-level models that do not contain any information about power consumption.

Conventionally, performance has been the primary design metric. Hence, high-level models that predict performance are more prevalent and more well understood than other types of high-level models. There are many research and entrepreneurial opportunities for people who can develop tools and/or languages for high-level models for estimating power, area, maximum clock speed, etc.