Verilog Awareness

Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ?
What is the difference between blocking and nonblocking assignment? Explain with a simple example?
What is the difference between wire and a reg data type?
Write code for async reset D-Flip-Flop, Shift Register.
Write code for 2:1 MUX using different coding styles.
Write code for parallel encoder and priority encoder.
Different "case" usage styles! Explain.
What is the difference between === and == ?
Why is defparam used for ?
What is the difference between unary operator and logical operator ?
What is the difference between task and function ?
What is the difference between transport and inertial delays?
What is the difference between casex and case statements ?
What is the difference between $monitor and $display ?
What is the difference between compiled, interpreted, event based and cycle based simulator ?