The Good, the Bad, and the Unsynthesizable - Interview Questions in vhdl

For each of the code fragments, answer whether the code is legal VHDL.
If the code is legal VHDL, answer whether it is synthesizable.
If the code is synthesizable:
answer whether it represents good coding practices.
answer whether the signal w or y is combinational, a latch, or a flip-flop.
If the the code is not legal, is not synthesizable, or does not follow good coding practices, explain why.
The signals are declared as follows:
a, b, c, d, w : std logic
m, y : unsigned(15 downto 0)
process (a, b) beginif a = '1' thenw <= b;end if;end process;
process (a, c) beginif a = '0' thenw <= c;end if;end process;
Answer:unsynth: single assignment rule — can't have multiple processes driving the same signal
process beginwait until rising_edge(a);w <= not w;end process;
Answer:good: w=flop // or bad coding style, because state machine without reset
b <= a;if b = '1' generatew <= c;end generate;if b = '0' generatew <= d;end generate;
Answer:illegal: dynamic test in generate
process beginw <= '0';wait until (a = '0');p: loopwait until rising_edge(b);next p when (a = '1');w <= c xor d;end loop;end process;
Answer:unsynth: different wait conditions
process (m) beginfor i in 15 downto 0 loopif 3 >= i theny(i) <= '0';elsey(i) <= m(i-3);end if;end loop;end process;
Answer:good: y = comb
process beginwait until rising_edge(a);if b = '1' thenwait until rising_edge(a);w <= b;elsew <= c;end if;end process;
Answer:good: w=flop