VHDL Interview Question(s)

What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect?
What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard?
For each of the architectures muruku 1. . . muruku 4, answer the following questions.
INSTRUCTIONS:
Is the code legal VHDL?
If the code is legal VHDL:
Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit.
Answer whether the code is synthesizable.
If the code is synthesizable, answer whether it adheres to good coding practices.If the the code is not legal, not synthesizable, or does not follow good coding practices, explain why.
entity sumit isport (a, b, clk : in std_logic;z : out std_logic);end schreyer;architecture main of sumit issignal m : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not m; end if; end process; end main;
Muruku 1
architecture muruku_1 of sumit issignal m : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; z <= not m; end if; end process; end muruku_1;
Muruku_X
architecture muruku_X of sumit issignal m, p : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= p; end if; end process; p <= not m; end muruku_X;
Muruku_2
architecture muruku_2 of sumit issignal m, p : std_logic;beginif (a or b) = ’1’ generatem <= ’1’; end generate; if (a or b) = ’0’ generate m <= ’0’; end generate; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not p; end if; end process; end muruku_2;
Muruku_3
architecture muruku_3 of sumit isbeginprocessbeginwait until rising_edge(clk);wait until rising_edge(clk);z <= not (a or b); end process; end muruku_3;
Muruku_4
architecture muruku_4 of sumit issignal m, p : std_logic;beginprocess ( clk )beginif rising_edge( clk ) thenm <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; z <= not p; end muruku_4;