Wire loading models contain all the information required by compile to estimate interconnect wiring delays.
A typical Wire load model definition contains: area, resistance, capacitance, slope and fanout. All these attributes are given per unit length wire. Slope value is used to characterize linear fanout.
Generally wire load models are used in ASIC design. These wire load models will contain statistical values which are used in pre-layout simulation of ASIC. Since we are extracting resistance(R), capacitance(C) values in back end after place and route(P&R) phase we need to perform pre-layout simulation before P&R.
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Monday, February 25, 2008
Wire load models
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