Terms of Digital Logic Metastability Definition

Definitions listed in Logical order.
Problem: Introducing an asynchronous signal into a digital {synchronized} system, using Flip-Flops.
The outcome is Intermittent or random failures during operation.

How to avoid metastability in ICs: Add an additional Flip Flop in the design to Synchronize the incoming
asynchronous signal with the new clock domain, which will reduce the Mean-Time-Between-Failure [MTBF].

Metastable: A state which exist between either "valid" digital logic state {an undefined voltage}

Digital Logic State: A defined range of voltages that indicate which logic level the device will switch to, or resides in.
For TTL, a logic low is {0 to .8 volts}, a logic high is {2.4 to 5 volts} [Logic Threshold Voltage Levels].

Undefined Voltage: A voltage between the established logic level, either High or Low; {.8 to 2.4 volts} from the example above.

Set-Up Time The time required for the input data signal at a flip flop to be valid before the incoming clock edge arrives .

Hold Time The time required for the input data signal to remain valid after the clock edge as transitioned.

Resolve Time: The amount of time the Flip Flop's output must return to a valid level before it's used.
This is 1/{clock frequency} - path delay. The output must be valid by the next clock, minus any chip or routing delay.
Path Delay = Tcko + Troute + Tsu;
.... Tcko = Clock to Output time of the flip flop,
.... Troute = Any trace delay between the the Q of the flip flop and the next device reading that data,
.... Tsu = any Set-Up time required by the next device reading the data.

Skew {Clock or data}: The change in time of one signal compared to another, caused by timing delays or
propagation delays. ~The timing differences developed by different devices performing the same function.

Ambiguity: The uncertainty in the amount of time it takes for a valid logic signal
to change from one state to another.

Metastability Window: The specific length of time, during which both the data
and clock should not occur. If both signals do occur, the output may go metastable.