Multi-Stage Synchronizer of Metastability.

Adding a second Flip Flop to the design will reduce the chance of the output going Metastable.
The output from the first flip flop may go valid, before the second flip flop is clocked. Adding yet another flip flop will reduce the probability that its output will be unstable even more. A 74AS4374 from TI provides a 'D' type, Dual stage synchronizer.

The table above details the difference in MTBF between a Single and Dual stage synchronizer.

The two graphs above, develop from a Texas Instruments Power Point presentation, details many of the standard TTL families.