PLDs
Keep in mind that the table below is some what dated, I'm sure the newer FPGAs and PLD ICs have MTBF [Mean-Time-Between-Failure] numbers which far exceed the ones listed. Checking the Cypress site (8/05) I see that their faster version of a 22V10 IC is a dash five (5 nS).
| Device | fmax (MHz) | | | |
| PALC16R8-25 | 28.5 | 9.503 | 0.515 | 14.68 |
| PALC20G10-20 | 41.6 | 3.73 | 0.173 | 4.91 |
| PALC20RA10-15 | 33.3 | 2.86 | 0.216 | 5.87 |
| PALC22V10C-10 | 90.9 | 0.00808 | 0.547 | 13.0 |
| PALC22V10B-15 | 50.0 | 55.76 | 0.261 | 8.19 |
| PALC22V10-20 | 41.6 | 0.125 | 0.190 | 4.73 |
| CY7C330-66 | 66.6 | 1.02 | 0.290 | 8.12 |
| CY7C331-20 | 31.2 | 298.0 | 0.184 | 5.91 |
| CY7C332-15 | 47.6 | 1.55 | 0.337 | 9.35 |
| CY7C344-20 | 41.6 | 966.0 | 0.223 | 7.55 |
The Table data was copied from "Determine PLD metastability to derive ample MTBFs",
EDN August 5 1991, Author: Sean Dingman.
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