FSM Questions of digital electronics

• Design an FSM that has 1 i/p and 1 o/p. The o/p becomes 1 and remains 1 when at least two 0's and two 1's have occurred as i/p's.
• Design a "%3" FSM that accepts one bit at a time, most significant bit first, and indicates if the number is divisible by 3.
• If an FSM is redesigned using a state register with minimum number of bits after connecting the output of a 3-state FSM to the inputs of an 9-state FSM, what is the maximum number of bits needed?