Comprehensive Verilog Tutorials

Chapter 1: Introduction & Overview of modules and proceduresChapter 2: Language Basics, Net & Register Data TypesChapter 3: Verilog Simulations & Display CommandsChapter 4: Continuous Assignments, Time Delays & TimescalesChapter 5: Verilog Operators, Timing Controls, Decisions & Looping StatementsChapter 6: RTL Models of Combinational Logic, Interactive DebuggingChapter 7: RTL models of Sequential Logic, Behavioral Models of RAMs & ROMsChapter 8: Modeling Structural DesignsChapter 9: Blocking & Non Blocking Assignments, State Machine DesignsChapter 10: File I/O, Test benches, Introduction to Synthesis Design FlowsChapter 11: Additional Behavioral Commands, Verilog Strength HandlingChapter 12: Verilog Gate Primitives, user defined PrimitivesChapter 13: Specify Blocks, SDF Back AnnotationChapter 14: Switch Primitives, Passive Device ModelingThanks to Jim Blake of Centillium, Raghav Santhanam of Synopsys & Pedro of Texas A&M University for the Tutorials and other numerous contributions.