Electronics Circuits Design

Friday, March 28, 2008

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Wednesday, March 5, 2008

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Tristate Buffers

You can think of tristate buffers as a way of turning a signal on and off. When the enable input at the top of the buffer is '1', the tristate buffer acts like a normal buffer. But when the enable input is '0', the buffer "turns off" by giving a very high impedance output. This effectively "disconnects" the buffer from the circuit. So if you need to turn off a signal, ground the enable input of the tristate buffer.

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Tip of the day - Board Design

Have you ever asked yourself the question: What should I do with the areas under the ICs?
My advise is: If you have a multilayer board then fill them with copper and connect it to GND, unless you have some very sensitive HF analog ICs where feedback is absolutely unwanted. Use at least two vias to the nearest GND layer and add one via for every square centimeter of copper area you have. This copper fill will give you a better shielding of your signals, the IC's will seem less noisy and less sensitive to EMI due to the tighter coupling to GND and you will get better compliance to the EMC standards.

However keep the areas under the ICs currentless - don't try to use them for decoupling or anything like this.

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This summary is not available. Please click here to view the post.

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Delay Locked Loop (DLL)

Why not a PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.

DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.

Advantages:

precision
stability
power management
noise sensitivity

jitter performance

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