When are DFT and Formal verification used?

DFT:

• manufacturing defects like stuck at "0" or "1".
• test for set of rules followed during the initial design stage.

Formal verification:

• Verification of the operation of the design, i.e, to see if the design follows spec.
• gate netlist == RTL (Equivalence checking)
• using mathematics and statistical analysis to check for eqivalence.