synthesizable Verilog from behavioral constructs - 1

Modifying a behavioural Verilog wait statement to make it synthesizable.Behavioural:command1;wait (x != 0);command3;Synthesizable:case (state)0 : begincommand1;if (x != 0) command3;else state <= 1;end1 : if (x != 0) // wait until this is truecommand3;endcaseYou also need to add the variable state, reg state. If a cycle delay between command1 and command3 does not matter, then the following is simpler, but not identical to the original:case (state)0 : begincommand1;state <= 1;end1 : if (x != 0) // wait until this is truecommand3;endcaseThe latter approach is preferred in many cases for coding simplicity.Note: in general commandi refers to a block of commands. It is assumed there is an appropriate clock for the case statement state machines. Care is required in setting appropriate reset states, initialization, and completion of use of a state machine:* Is there a signal to tell the state machine to begin?* Does a done signal go high, signalling the state machine has finished?* When it is not in operation, does the state machine idle correctly? Does it change signal values shared with other code? Does it set outputs from it to appropriate idling values?* Is the state machine reset to the idle state by a reset signal?* Ensure that you initialize all registers.* Ensure that your state register has the correct bit width - if it is too small, assigning a larger state value will just return it to an earlier state.